[ Teaching ] [ Research ] [ Service ]

Abdel Ejnioui received the Bachelor of Engineering Technology, the Master of Science in Computer Sciences, and the Ph.D. degree in Computer Sciences and Engineering from the University of South Florida in 1992, 1995, and 1999 respectively.  From 2001 to 2005, he was an Assistant Professor in the Electrical and Computer Engineering Dept. of the University of Central Florida.  Since summer 2005, he has been serving as an Assistant Professor in the Department of Information Technology at the University of South Florida.  Upon completion of his Ph.D. degree, he worked as a Principal Software Engineer at Avant! Corp. before being acquired by Synopsys Corp.  Previously, he held several positions in the information technology industry between Central and West Florida.             

Abdel's research includes computer architecture with emphasis on reconfigurable computing, configurable processors, parallel processing, and VLSI design.  He is a member of the IEEE and the IEEE Computer Society.

Course Teaching

Currently, Abdel teaches the following courses:

· COP 2510 Programming Concepts 

· ETG 4931 Advanced Java

· CDA 3101 Computer Organization

· EEL 4782 Computer Networks

· EEL 4854 Data Structures

· ETG 4932 Discrete Mathematical Structures

In the past, he taught the following graduate courses:

· EEL 5708 High Performance Architecture

· EEL 5704 Computer-Aided Logic Design

· EEL 5722 FPGA Design

· EEL 5935 Java Programming

· EEL 6327 Synthesis of VLSI Circuits

· EEL 6707 Parallel Processing

He also taught the following undergraduate courses:

· CDA 4203 Computer System Design

· CEN 4020 Software Engineering

· COT 3100 Discrete Structures

· EEL 3342 Introduction to Digital Circuits and Systems

· EEL 4882 Engineering Systems Software

Student Advising

Abdel served as a graduate advisor to the following students:

· Anuja J. Thakkar, Pipelining of Double Precision Floating Point Low-Radix Digit-Recurrence Arithmetic Algorithms on FPGAs, M.S. Thesis, Dept. of Electrical and Computer Engineering, Spring 2006.

· Rashad Oreifej, Synthesis of Self-Resetting Stage Logic Pipelines, M.S. Thesis, Dept. of Electrical and Computer Engineering, UCF, Summer 2006, Currently a Ph.D Student at UCF, Orlando, Florida.

· Abdelhalim M. Alsharqawi, Design and Synthesis of Clockless Pipelines Based on Self-Resetting Stage Logic, Ph.D. Dissertation, Dept. of Electrical and Computer Engineering, UCF, Fall 2005, Currently at Texas Instruments, Dallas, Texas.

· Todd E. Person, FPGA-Based Design of a Maximum-Power Tracking System for Space Applications, M.S. Thesis, Dept. of Electrical and Computer Engineering, UCF, Fall 2004, Currently at New York University, New York, N.Y.

· Michael Lomonaco, CRYPTARRAY: A Scalable and Reconfigurable Architecture for Cryptographic Applications, M.S. Thesis, Dept. of Electrical and Computer Engineering, UCF, Summer 2004, Currently at Northrop Grumann, Sacramento, California.

· Ravi K. Namballa, CHESS: A Tool for CDFG Extraction and High-Level Synthesis of VLSI Systems, M.S. Thesis, Co-advisor, Dept. of Computer Sciences and Engineering, USF, Summer 2003.

· Sitaraman Krishna, A VLSI Architecture for Object Recognition using Tree Matching, M.S. Thesis, Co-advisor, Dept. of Computer Sciences and Engineering, USF, Fall 2001.

Research Interests

Abdel's research interests include reconfigurable computing, configurable computer architecture, parallel processing, and VLSI design.

Publications

Journal Publications                                                         

R. DeMara, Y. Tseng, A. Ejnioui, "Tiered Algorithm for Distributed Process Quiescence and Termination Detection." To appear in the IEEE Transactions on Distributed and Parallel Processing.

R. DeMara, Y. Tseng, K. Drake, A. Ejnioui, "Capability Classes of Multiprocessor Synchronization Techniques," International Journal of Computer and Applications, vol. 28, no. 4, October 2006, pp. 1757-1804.

A. Ejnioui, N. Ranganathan, “Routing on Field-Programmable Switch Matrices,” IEEE Transactions on VLSI Systems, vol. 11, no. 2, April 2003, pp. 283-287.

A. Ejnioui, N. Ranganathan, “Multi-terminal Net Routing for Partial Crossbar-Based Multi-FPGA Systems,” IEEE Transactions on VLSI Systems, vol. 11, no. 1, February 2003, pp. 71-78.

A. Ejnioui, N. Ranganathan, “A Partitioning Algorithm for Technology-Mapped Designs on Single-Chip Emulation Systems,” IEEE Transactions on VLSI Systems, vol. 9, no. 2, April 2001, pp. 407-410.

V. Krishna, N. Ranganathan, A. Ejnioui, “A Tree Matching Chip,” IEEE Transactions on VLSI Systems, vol. 7, no. 2, June 1999, pp. 277-280.

Conference Publications

A. Ejnioui, P. Bao, "Hardware Acceleration of the Generalized Finite Automata Algorithm," International Conference on Computer Design, Las Vegas, Nevada, June 2007.

A. Ejnioui, "Prototyping of a Two-Phase Micropipeline on FPGAs," International Conference on Reconfigurable Systems and Algorithms, Las Vegas, Nevada, pp. 138-144, June 2007.

A. Ejnioui, "FPGA Prototyping of a Two-Phase Self-Oscillating Micropipeline," IEEE Computer Society Annual Symposium on VLSI, Puerto Oro, Brazil, pp. 437-438, May 2007.

A. Karshmer, A. Ejnioui, "MathOMatic Blocks: An Automated Tactile, Interactive Method of Teaching Mathematics to Blind Studens in the K-12 Environment," CSUN Conference, Northridge, California, Spring 2007.

H. Tan, R. F. DeMara, A. J. Thakkar, A. Ejnioui, J. D. Sattler, "Complexity Performance Evaluation of Two Partial Reconfiguration Interfaces on FPGAs: A Case Study," International Conference on Engineering of Reconfigurable Systems and Algorithms, Las Vegas, Nevada, June 2006.

R. Oreifej, A. Alsharqawi, A. Ejnioui, "Synthesis of Pipelined SRSL Circuits," IEEE Computer Society Annual Symposium on VLSI, Karlsruhe, Germany, March 2006.

A. J. Thakkar, A. Ejnioui, "Pipelining of Double Precision Floating Point Division and Square Root Operations," ACM Southeast Regional Conference, Melbourne, Florida, March 2006.

A. J. Thakkar, A. Ejnioui, “Design and Implementation of Double Precision Floating Point Division and Square Root on FPGAs,” IEEE Aerospace Conference, Big Sky, Montana, March 2006.

R. Oreifej, A. Alsharqawi, A. Ejnioui, “Pipeline Synthesis of SRSL Circuits,” IEEE International Conference on Electronics, Circuits, and Systems, Gammarth, Tunisia, December 2005.

A. Alsharqawi, A. Ejnioui, “SRSL Pipelining of Coarse-Grain Datapaths,” IEEE International Conference on Electronics, Circuits, and Systems, Gammarth, Tunisia, December 2005.

A. Alsharqawi, A. Ejnioui, “Clockless Pipelining for Coarse-Grain Datapaths”, International Conference on VLSI Design, Hyderabad, India, January 2006.

A. Ejnioui, R. DeMara, “Area Reclamation Strategies and Metrics for SRAM-Based Reconfigurable Devices,” International Conference on Engineering of Reconfigurable Systems and Algorithms, Las Vegas, Nevada, pp. 196-202, June 2005.

A.  Alsharqawi, A. Ejnioui, “Synthesis of Self-Resetting Stage Logic Pipelines,” IEEE Computer Society Annual Symposium on VLSI, St. Petersburg, Florida, pp. 260-262, May 2005.

A. Ejnioui, A. Alsharqawi, “Pipeline-Level Control of Self-Resetting Pipelines,” Euromicro Symposium on Digital System Design, Rennes, France, pp. 342-349, September 2004.

A. Ejnioui, A. Alsharqawi, “Pipeline-Level Control of Self-Resetting Stage Logic Pipelines,” IEEE Northeast Workshop on Circuits and Systems, Montreal, Canada, pp. 389-392, June 2004.

A. Ejnioui, A. Alsharqawi, “A Clockless Reconfigurable Array Based on Self-Resetting Logic,” World Multiconference on Systemics, Cybernetics, and Informatics, Orlando, Florida, vol. 11, pp. 61-66, June 2004.

A. Ejnioui, A. Alsharqawi, “Self-Resetting Stage Logic Pipelines,” ACM Great Lakes Symposium on VLSI, Boston, Massachusetts, pp. 174-177, April 2004.

A. Ejnioui, A. Alsharqawi, “Pipeline Design Based on Self-Resetting Stage Logic,” IEEE Computer Society Annual Symposium on VLSI, Lafayette, Louisiana, pp. 254-257, February 2004.

A. Ejnioui, A. Rhiati, “A Reconfigurable Memory Management Core for Java Applications,” IEEE Computer Society Annual Symposium on VLSI, Lafayette, Louisiana, pp. 309-312, February 2004.

R. Namballa, N. Ranganathan, A. Ejnioui, “Control and Data-Flow Graph Extraction for High-Level Synthesis,” IEEE Computer Society Annual Symposium on VLSI, Lafayette, Louisiana, pp. 187-192, February 2004.

K. Sitaraman, A. Ejnioui, N. Ranganathan, “A Parallel Algorithm and Architecture for Object Recognition in Images,” IEEE Computer Architecture for Machine Perception, New Orleans, Louisiana, April 2003.

W. Kuang, J. S. Yuan, A. Ejnioui, “Supply Voltage Scalable System Design Using Self-Timed Circuits,” IEEE Computer Society Annual Symposium on VLSI, Pittsburg, Pennsylvania, pp. 161-166, February 2003.

S. Krishna, N. Ranganathan, A. Ejnioui, “A VLSI Architecture for Object Recognition Using Tree Matching,” International Conference on Application-Specific Systems, Architectures and Processors, San Jose, California, pp. 325-334, July 2002.

A. Ejnioui, N. Ranganathan, “Routing on Switch Matrix FPGAs,” International Conference on VLSI Design, Calcutta, India, pp. 248-253, January 2000.

A. Ejnioui, N. Ranganathan, “Design Partitioning on Single-Chip Emulation Systems,” International Conference on VLSI Design, Calcutta, India, pp. 234-239, January 2000.

A. Ejnioui, N. Ranganathan, “Multi-Terminal Net Routing for Partial Crossbar-Based Multi-FPGA Systems,” ACM International Symposium on FPGAs, Monterey, California, pp. 176-184, February 1999.

V. Krishna, A. Ejnioui, N. Ranganathan, “A Tree Matching Chip,” International Conference on VLSI Design, Bangalore, India, pp. 280-285, January 1996.

A. Ejnioui, N. Ranganathan, “Systolic Algorithms for Tree Pattern Matching,” International Conference on Computer Design: VLSI in Computers and Processors, Austin, Texas, pp 650-655, October 1995.

Member of the Curriculum Committee of the Information Technology Dept. at USF Lakeland

Reviewer for IEEE Transactions on VLSI; IEEE Transactions on Circuits and Systems for Video Technology; IEE Proceedings on Circuits, Devices, and Systems; Journal of Applied Systems Studies; Journal of Mathematical and Computer Modeling; International Symposium on Low Power and Electronic Design; International Conference on Computer Design; International VLSI Design Conference.

Finance Chair for the IEEE Computer Society Annual Symposium on VLSI

Member of the IEEE and the IEEE Computer Society

Member of F K F